Image from Google Jackets

Verilog digital system design :RT level synthesis, testbench, and verification / Zainalabedin Navabi.

By: Material type: TextTextSeries: McGraw-Hill electronic engineering seriesPublication details: New Delhi McGraw-Hill, 2008Edition: 2nd edISBN:
  • 9780070252219
Subject(s): DDC classification:
  • 621.39NAV-V2 22
Online resources:
Tags from this library: No tags from this library for this title. Log in to add tags.
Holdings
Item type Current library Call number Status Barcode
TEQIP Reference TEQIP Reference CENTRAL LIBRARY Reference 621.39NAV-V2 Not for loan T0678
TEQIP Books TEQIP Books CENTRAL LIBRARY General Stacks 621.39NAV-V2 Available T0679
TEQIP Books TEQIP Books CENTRAL LIBRARY General Stacks 621.39NAV-V2 Available T0680
TEQIP Books TEQIP Books CENTRAL LIBRARY General Stacks 621.39NAV-V2 Available T0681
Total holds: 0

Includes bibliographical references and index.

Share
Powered by Koha ILS
Page Design & Customization: Library Web Team CE Thalassery