Digital System Design with SystemVerilog.
Zwolinski.
Digital System Design with SystemVerilog. - 1 online resource (403 pages)
Cover -- Contents -- List of Figures -- List of Tables -- Preface -- Acknowledgments -- About the Author -- 1. Introduction -- 1.1 Modern Digital Design -- 1.2 Designing with Hardware Description Languages -- 1.2.1 Design Automation -- 1.2.2 What is SystemVerilog? -- 1.2.3 What is VHDL? -- 1.2.4 Simulation -- 1.2.5 Synthesis -- 1.2.6 Reusability -- 1.2.7 Verification -- 1.2.8 Design Flow -- 1.3 CMOS Technology -- 1.3.1 Logic Gates -- 1.3.2 ASICs and FPGAs -- 1.4 Programmable Logic -- 1.5 Electrical Properties -- 1.5.1 Noise Margins -- 1.5.2 Fan-Out -- Summary -- Further Reading -- Exercises -- 2. Combinational Logic Design -- 2.1 Boolean Algebra -- 2.1.1 Values -- 2.1.2 Operators -- 2.1.3 Truth Tables -- 2.1.4 Rules of Boolean Algebra -- 2.1.5 De Morgan's Law -- 2.1.6 Shannon's Expansion Theorem -- 2.2 Logic Gates -- 2.3 Combinational Logic Design -- 2.3.1 Logic Minimization -- 2.3.2 Karnaugh Maps -- 2.4 Timing -- 2.5 Number Codes -- 2.5.1 Integers -- 2.5.2 Fixed Point Numbers -- 2.5.3 Floating Point Numbers -- 2.5.4 Alphanumeric Characters -- 2.5.5 Gray Codes -- 2.5.6 Parity Bits -- Summary -- Further Reading -- Exercises -- 3. Combinational Logic Using SystemVerilog Gate Models -- 3.1 Modules and Files -- 3.2 Identifiers, Spaces, and Comments -- 3.3 Basic Gate Models -- 3.4 A Simple Netlist -- 3.5 Logic Values -- 3.6 Continuous Assignments -- 3.6.1 SystemVerilog Operators -- 3.7 Delays -- 3.8 Parameters -- 3.9 Testbenches -- Summary -- Further Reading -- Exercises -- 4. Combinational Building Blocks -- 4.1 Multiplexers -- 4.1.1 2 to 1 Multiplexer -- 4.1.2 4 to 1 Multiplexer -- 4.2 Decoders -- 4.2.1 2 to 4 Decoder -- 4.2.2 Parameterizable Decoder -- 4.2.3 Seven-Segment Decoder -- 4.3 Priority Encoder -- 4.3.1 Don't Cares and Uniqueness -- 4.4 Adders -- 4.4.1 Functional Model -- 4.4.2 Ripple Adder -- 4.4.3 Tasks -- 4.5 Parity Checker. 4.6 Three-State Buffers -- 4.6.1 Multi-Valued Logic -- 4.7 Testbenches for Combinational Blocks -- Summary -- Further Reading -- Exercises -- 5. SystemVerilog Models of Sequential Logic Blocks -- 5.1 Latches -- 5.1.1 SR Latch -- 5.1.2 D Latch -- 5.2 Flip-Flops -- 5.2.1 Edge-Triggered D Flip-Flop -- 5.2.2 Asynchronous Set and Reset -- 5.2.3 Synchronous Set and Reset and Clock Enable -- 5.3 JK and T Flip-Flops -- 5.4 Registers and Shift Registers -- 5.4.1 Multiple Bit Register -- 5.4.2 Shift Registers -- 5.5 Counters -- 5.5.1 Binary Counter -- 5.5.2 Johnson Counter -- 5.5.3 Linear Feedback Shift Register -- 5.6 Memory -- 5.6.1 ROM -- 5.6.2 SRAM -- 5.6.3 Synchronous RAM -- 5.7 Sequential Multiplier -- 5.8 Testbenches for Sequential Building Blocks -- 5.8.1 Clock Generation -- 5.8.2 Reset and Other Deterministic Signals -- 5.8.3 Checking Responses -- Summary -- Further Reading -- Exercises -- 6. Synchronous Sequential Design -- 6.1 Synchronous Sequential Systems -- 6.2 Models of Synchronous Sequential Systems -- 6.2.1 Moore and Mealy Machines -- 6.2.2 State Registers -- 6.2.3 Design of a Three-Bit Counter -- 6.3 Algorithmic State Machines -- 6.4 Synthesis from ASM Charts -- 6.4.1 Hardware Implementation -- 6.4.2 State Assignment -- 6.4.3 State Minimization -- 6.5 State Machines in SystemVerilog -- 6.5.1 A First Example -- 6.5.2 A Sequential Parity Detector -- 6.5.3 Vending Machine -- 6.5.4 Storing Data -- 6.6 Testbenches for State Machines -- Summary -- Further Reading -- Exercises -- 7. Complex Sequential Systems -- 7.1 Linked State Machines -- 7.2 Datapath/Controller Partitioning -- 7.3 Instructions -- 7.4 A Simple Microprocessor -- 7.5 SystemVerilog Model of a Simple Microprocessor -- Summary -- Further Reading -- Exercises -- 8. Writing Testbenches -- 8.1 Basic Testbenches -- 8.1.1 Clock Generation -- 8.1.2 Reset and Other Deterministic Signals. 8.1.3 Monitoring Responses -- 8.1.4 Dumping Responses -- 8.1.5 Test Vectors from a File -- 8.2 Testbench Structure -- 8.2.1 Programs -- 8.3 Constrained Random Stimulus Generation -- 8.3.1 Object-Oriented Programming -- 8.3.2 Randomization -- 8.4 Assertion-Based Verification -- Summary -- Further Reading -- Exercises -- 9. SystemVerilog Simulation -- 9.1 Event-Driven Simulation -- 9.2 SystemVerilog Simulation -- 9.3 Races -- 9.3.1 Avoiding Races -- 9.4 Delay Models -- 9.5 Simulator Tools -- Summary -- Further Reading -- Exercises -- 10. SystemVerilog Synthesis -- 10.1 RTL Synthesis -- 10.1.1 Non-Synthesizable SystemVerilog -- 10.1.2 Inferred Flip-Flops and Latches -- 10.1.3 Combinational Logic -- 10.1.4 Summary of RTL Synthesis Rules -- 10.2 Constraints -- 10.2.1 Attributes -- 10.2.2 Area and Structural Constraints -- 10.2.3 full_case and parallel_case Attributes -- 10.3 Synthesis for FPGAs -- 10.4 Behavioral Synthesis -- 10.5 Verifying Synthesis Results -- 10.5.1 Timing Simulation -- Summary -- Further Reading -- Exercises -- 11. Testing Digital Systems -- 11.1 The Need for Testing -- 11.2 Fault Models -- 11.2.1 Single-Stuck Fault Model -- 11.2.2 PLA Faults -- 11.3 Fault-Oriented Test Pattern Generation -- 11.3.1 Sensitive Path Algorithm -- 11.3.2 Undetectable Faults -- 11.3.3 The D Algorithm -- 11.3.4 PODEM -- 11.3.5 Fault Collapsing -- 11.4 Fault Simulation -- 11.4.1 Parallel Fault Simulation -- 11.4.2 Concurrent Fault Simulation -- Summary -- Further Reading -- Exercises -- 12. Design for Testability -- 12.1 Ad hoc Testability Improvements -- 12.2 Structured Design for Test -- 12.3 Built-In Self-Test -- 12.3.1 Example -- 12.3.2 Built-In Logic Block Observation (BILBO) -- 12.4 Boundary Scan (IEEE 1149.1) -- Summary -- Further Reading -- Exercises -- 13. Asynchronous Sequential Design -- 13.1 Asynchronous Circuits. 13.2 Analysis of Asynchronous Circuits -- 13.2.1 Informal Analysis -- 13.2.2 Formal Analysis -- 13.3 Design of Asynchronous Circuits -- 13.4 Asynchronous State Machines -- 13.5 Setup and Hold Times and Metastability -- 13.5.1 The Fundamental Mode Restriction and Synchronous Circuits -- 13.5.2 SystemVerilog Modeling of Setup and Hold Time Violations -- 13.5.3 Metastability -- Summary -- Further Reading -- Exercises -- 14. Interfacing with the Analog World -- 14.1 Digital-to-Analog Converters -- 14.2 Analog-to-Digital Converters -- 14.3 Verilog-AMS -- 14.3.1 Verilog-AMS Fundamentals -- 14.3.2 Contribution Statements -- 14.3.3 Mixed-Signal Modeling -- 14.4 Phased-Locked Loops -- 14.5 Verilog-AMS Simulators -- Summary -- Further Reading -- Exercises -- A. SystemVerilog and Verilog -- A.1 Standards -- A.2 SystemVerilog and Verilog Differences -- Answers to Selected Exercises -- Bibliography -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- Q -- R -- S -- T -- U -- V -- W -- X.
9788131744529
Electronic books.
621.39
Digital System Design with SystemVerilog. - 1 online resource (403 pages)
Cover -- Contents -- List of Figures -- List of Tables -- Preface -- Acknowledgments -- About the Author -- 1. Introduction -- 1.1 Modern Digital Design -- 1.2 Designing with Hardware Description Languages -- 1.2.1 Design Automation -- 1.2.2 What is SystemVerilog? -- 1.2.3 What is VHDL? -- 1.2.4 Simulation -- 1.2.5 Synthesis -- 1.2.6 Reusability -- 1.2.7 Verification -- 1.2.8 Design Flow -- 1.3 CMOS Technology -- 1.3.1 Logic Gates -- 1.3.2 ASICs and FPGAs -- 1.4 Programmable Logic -- 1.5 Electrical Properties -- 1.5.1 Noise Margins -- 1.5.2 Fan-Out -- Summary -- Further Reading -- Exercises -- 2. Combinational Logic Design -- 2.1 Boolean Algebra -- 2.1.1 Values -- 2.1.2 Operators -- 2.1.3 Truth Tables -- 2.1.4 Rules of Boolean Algebra -- 2.1.5 De Morgan's Law -- 2.1.6 Shannon's Expansion Theorem -- 2.2 Logic Gates -- 2.3 Combinational Logic Design -- 2.3.1 Logic Minimization -- 2.3.2 Karnaugh Maps -- 2.4 Timing -- 2.5 Number Codes -- 2.5.1 Integers -- 2.5.2 Fixed Point Numbers -- 2.5.3 Floating Point Numbers -- 2.5.4 Alphanumeric Characters -- 2.5.5 Gray Codes -- 2.5.6 Parity Bits -- Summary -- Further Reading -- Exercises -- 3. Combinational Logic Using SystemVerilog Gate Models -- 3.1 Modules and Files -- 3.2 Identifiers, Spaces, and Comments -- 3.3 Basic Gate Models -- 3.4 A Simple Netlist -- 3.5 Logic Values -- 3.6 Continuous Assignments -- 3.6.1 SystemVerilog Operators -- 3.7 Delays -- 3.8 Parameters -- 3.9 Testbenches -- Summary -- Further Reading -- Exercises -- 4. Combinational Building Blocks -- 4.1 Multiplexers -- 4.1.1 2 to 1 Multiplexer -- 4.1.2 4 to 1 Multiplexer -- 4.2 Decoders -- 4.2.1 2 to 4 Decoder -- 4.2.2 Parameterizable Decoder -- 4.2.3 Seven-Segment Decoder -- 4.3 Priority Encoder -- 4.3.1 Don't Cares and Uniqueness -- 4.4 Adders -- 4.4.1 Functional Model -- 4.4.2 Ripple Adder -- 4.4.3 Tasks -- 4.5 Parity Checker. 4.6 Three-State Buffers -- 4.6.1 Multi-Valued Logic -- 4.7 Testbenches for Combinational Blocks -- Summary -- Further Reading -- Exercises -- 5. SystemVerilog Models of Sequential Logic Blocks -- 5.1 Latches -- 5.1.1 SR Latch -- 5.1.2 D Latch -- 5.2 Flip-Flops -- 5.2.1 Edge-Triggered D Flip-Flop -- 5.2.2 Asynchronous Set and Reset -- 5.2.3 Synchronous Set and Reset and Clock Enable -- 5.3 JK and T Flip-Flops -- 5.4 Registers and Shift Registers -- 5.4.1 Multiple Bit Register -- 5.4.2 Shift Registers -- 5.5 Counters -- 5.5.1 Binary Counter -- 5.5.2 Johnson Counter -- 5.5.3 Linear Feedback Shift Register -- 5.6 Memory -- 5.6.1 ROM -- 5.6.2 SRAM -- 5.6.3 Synchronous RAM -- 5.7 Sequential Multiplier -- 5.8 Testbenches for Sequential Building Blocks -- 5.8.1 Clock Generation -- 5.8.2 Reset and Other Deterministic Signals -- 5.8.3 Checking Responses -- Summary -- Further Reading -- Exercises -- 6. Synchronous Sequential Design -- 6.1 Synchronous Sequential Systems -- 6.2 Models of Synchronous Sequential Systems -- 6.2.1 Moore and Mealy Machines -- 6.2.2 State Registers -- 6.2.3 Design of a Three-Bit Counter -- 6.3 Algorithmic State Machines -- 6.4 Synthesis from ASM Charts -- 6.4.1 Hardware Implementation -- 6.4.2 State Assignment -- 6.4.3 State Minimization -- 6.5 State Machines in SystemVerilog -- 6.5.1 A First Example -- 6.5.2 A Sequential Parity Detector -- 6.5.3 Vending Machine -- 6.5.4 Storing Data -- 6.6 Testbenches for State Machines -- Summary -- Further Reading -- Exercises -- 7. Complex Sequential Systems -- 7.1 Linked State Machines -- 7.2 Datapath/Controller Partitioning -- 7.3 Instructions -- 7.4 A Simple Microprocessor -- 7.5 SystemVerilog Model of a Simple Microprocessor -- Summary -- Further Reading -- Exercises -- 8. Writing Testbenches -- 8.1 Basic Testbenches -- 8.1.1 Clock Generation -- 8.1.2 Reset and Other Deterministic Signals. 8.1.3 Monitoring Responses -- 8.1.4 Dumping Responses -- 8.1.5 Test Vectors from a File -- 8.2 Testbench Structure -- 8.2.1 Programs -- 8.3 Constrained Random Stimulus Generation -- 8.3.1 Object-Oriented Programming -- 8.3.2 Randomization -- 8.4 Assertion-Based Verification -- Summary -- Further Reading -- Exercises -- 9. SystemVerilog Simulation -- 9.1 Event-Driven Simulation -- 9.2 SystemVerilog Simulation -- 9.3 Races -- 9.3.1 Avoiding Races -- 9.4 Delay Models -- 9.5 Simulator Tools -- Summary -- Further Reading -- Exercises -- 10. SystemVerilog Synthesis -- 10.1 RTL Synthesis -- 10.1.1 Non-Synthesizable SystemVerilog -- 10.1.2 Inferred Flip-Flops and Latches -- 10.1.3 Combinational Logic -- 10.1.4 Summary of RTL Synthesis Rules -- 10.2 Constraints -- 10.2.1 Attributes -- 10.2.2 Area and Structural Constraints -- 10.2.3 full_case and parallel_case Attributes -- 10.3 Synthesis for FPGAs -- 10.4 Behavioral Synthesis -- 10.5 Verifying Synthesis Results -- 10.5.1 Timing Simulation -- Summary -- Further Reading -- Exercises -- 11. Testing Digital Systems -- 11.1 The Need for Testing -- 11.2 Fault Models -- 11.2.1 Single-Stuck Fault Model -- 11.2.2 PLA Faults -- 11.3 Fault-Oriented Test Pattern Generation -- 11.3.1 Sensitive Path Algorithm -- 11.3.2 Undetectable Faults -- 11.3.3 The D Algorithm -- 11.3.4 PODEM -- 11.3.5 Fault Collapsing -- 11.4 Fault Simulation -- 11.4.1 Parallel Fault Simulation -- 11.4.2 Concurrent Fault Simulation -- Summary -- Further Reading -- Exercises -- 12. Design for Testability -- 12.1 Ad hoc Testability Improvements -- 12.2 Structured Design for Test -- 12.3 Built-In Self-Test -- 12.3.1 Example -- 12.3.2 Built-In Logic Block Observation (BILBO) -- 12.4 Boundary Scan (IEEE 1149.1) -- Summary -- Further Reading -- Exercises -- 13. Asynchronous Sequential Design -- 13.1 Asynchronous Circuits. 13.2 Analysis of Asynchronous Circuits -- 13.2.1 Informal Analysis -- 13.2.2 Formal Analysis -- 13.3 Design of Asynchronous Circuits -- 13.4 Asynchronous State Machines -- 13.5 Setup and Hold Times and Metastability -- 13.5.1 The Fundamental Mode Restriction and Synchronous Circuits -- 13.5.2 SystemVerilog Modeling of Setup and Hold Time Violations -- 13.5.3 Metastability -- Summary -- Further Reading -- Exercises -- 14. Interfacing with the Analog World -- 14.1 Digital-to-Analog Converters -- 14.2 Analog-to-Digital Converters -- 14.3 Verilog-AMS -- 14.3.1 Verilog-AMS Fundamentals -- 14.3.2 Contribution Statements -- 14.3.3 Mixed-Signal Modeling -- 14.4 Phased-Locked Loops -- 14.5 Verilog-AMS Simulators -- Summary -- Further Reading -- Exercises -- A. SystemVerilog and Verilog -- A.1 Standards -- A.2 SystemVerilog and Verilog Differences -- Answers to Selected Exercises -- Bibliography -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- Q -- R -- S -- T -- U -- V -- W -- X.
9788131744529
Electronic books.
621.39