MARC details
| 000 -LEADER |
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| fixed length control field |
10640nam a22003733i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
EBC5125872 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20190104160519.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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| fixed length control field |
m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
181231s1999 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9788131740583 |
| Qualifying information |
(electronic bk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(MiAaPQ)EBC5125872 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(Au-PeEL)EBL5125872 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaONFJC)MIL266295 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)1024275675 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
MiAaPQ |
| Language of cataloging |
eng |
| Description conventions |
rda |
| -- |
pn |
| Transcribing agency |
MiAaPQ |
| Modifying agency |
MiAaPQ |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Edition number |
23rd |
| Classification number |
621.392 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Crouch, Alfred L. |
| 245 10 - TITLE STATEMENT |
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| Title |
Design-For-Test For Digital Ic'S And Embedded Core Systems. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
1 online resource (378 pages) |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Cover -- Contents -- Preface -- Acknowledgments -- Introduction -- 1 Test and Design-for-Test Fundamentals -- 1.1 Introduction to Test and DFT Fundamentals -- 1.1.1 Purpose -- 1.1.2 Introduction to Test, the Test Process, and Design-for-Test -- 1.1.3 Concurrent Test Engineering -- 1.2 The Reasons for Testing -- 1.2.1 Why Test? Why Add Test Logic? -- 1.2.2 Pro and Con Perceptions of DFT -- 1.3 The Definition of Testing -- 1.3.1 What Is Testing? -- 1.3.2 Stimulus -- 1.3.3 Response -- 1.4 Test Measurement Criteria -- 1.4.1 What Is Measured? -- 1.4.2 Fault Metric Mathematics -- 1.5 Fault Modeling -- 1.5.1 Physical Defects -- 1.5.2 Fault Modeling -- 1.6 Types of Testing -- 1.6.1 Functional Testing -- 1.6.2 Structural Testing -- 1.6.3 Combinational Exhaustive and Pseudo-Exhaustive Testing -- 1.6.4 Full Exhaustive Testing -- 1.6.5 Test Styles -- 1.7 Manufacturing Test -- 1.7.1 The Manufacturing Test Process -- 1.7.2 Manufacturing Test Load Board -- 1.7.3 Manufacturing Test Program -- 1.8 Using Automatic Test Equipment -- 1.8.1 Automatic Test Equipment -- 1.8.2 ATE Limitations -- 1.8.3 ATE Cost Considerations -- 1.9 Test and Pin Timing -- 1.9.1 Tester and Device Pin Timing -- 1.9.2 Tester Edge Sets -- 1.9.3 Tester Precision and Accuracy -- 1.10 Manufacturing Test Program Components -- 1.10.1 The Pieces and Parts of a Test Program -- 1.10.2 Test Program Optimization -- 1.11 Recommended Reading -- 2 Automatic Test Pattern Generation Fundamentals -- 2.1 Introduction to Automatic Test Pattern Generation -- 2.1.1 Purpose -- 2.1.2 Introduction to Automated Test Pattern Generation -- 2.1.3 The Vector Generation Process Flow -- 2.2 The Reasons for ATPG -- 2.2.1 Why ATPG? -- 2.2.2 Pro and Con Perceptions of ATPG -- 2.3 The Automatic Test Pattern Generation Process -- 2.3.1 Introduction to ATPG -- 2.4 Introducing the Combinational Stuck-At Fault. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
2.4.1 Combinational Stuck-At Faults -- 2.4.2 Combinational Stuck-At Fault Detection -- 2.5 Introducing the Delay Fault -- 2.5.1 Delay Faults -- 2.5.2 Delay Fault Detection -- 2.6 Introducing the Current-Based Fault -- 2.6.1 Current-Based Testing -- 2.6.2 Current-Based Testing Detection -- 2.7 Testability and Fault Analysis Methods -- 2.7.1 Why Conduct ATPG Analysis or Testability Analysis? -- 2.7.2 What Types of Testability Analysis Are Available? -- 2.7.3 Fault Effective Circuits -- 2.7.4 Controllability-Observability Analysis -- 2.7.5 Circuit Learning -- 2.8 Fault Masking -- 2.8.1 Causes and Effects of Fault Masking -- 2.8.2 Fault Masking on Various Fault Models -- 2.9 Stuck Fault Equivalence -- 2.9.1 Fault Equivalence Optimization -- 2.9.2 Fault Equivalence Side Effects -- 2.10 Stuck-At ATPG -- 2.10.1 Fault Selection -- 2.10.2 Exercising the Fault -- 2.10.3 Detect Path Sensitization -- 2.11 Transition Delay Fault ATPG -- 2.11.1 Using ATPG with Transition Delay Faults -- 2.11.2 Transition Delay Is a Gross Delay Fault -- 2.12 Path Delay Fault ATPG -- 2.12.1 Path Delay ATPG -- 2.12.2 Robust Fault Detection -- 2.12.3 The Path Delay Design Description -- 2.12.4 Path Enumeration -- 2.13 Current-Based Fault ATPG -- 2.13.1 Current-Based ATPG Algorithms -- 2.14 Combinational versus Sequential ATPG -- 2.14.1 Multiple Cycle Sequential Test Pattern Generation -- 2.14.2 Multiple Time Frame Combinational ATPG -- 2.14.3 Two-Time-Frame ATPG Limitations -- 2.14.4 Cycle-Based ATPG Limitations -- 2.15 Vector Simulation -- 2.15.1 Fault Simulation -- 2.15.2 Simulation for Manufacturing Test -- 2.16 ATPG Vectors -- 2.16.1 Vector Formats -- 2.16.2 Vector Compaction and Compression -- 2.17 ATPG-Based Design Rules -- 2.17.1 The ATPG Tool "NO" Rules List -- 2.17.2 Exceptions to the Rules -- 2.18 Selecting an ATPG Tool -- 2.18.1 The Measurables. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
2.18.2 The ATPG Benchmark Process -- 2.19 ATPG Fundamentals Summary -- 2.19.1 Establishing an ATPG Methodology -- 2.20 Recommended Reading -- 3 Scan Architectures and Techniques -- 3.1 Introduction to Scan-Based Testing -- 3.1.1 Purpose -- 3.1.2 The Testing Problem -- 3.1.3 Scan Testing -- 3.1.4 Scan Testing Misconceptions -- 3.2 Functional Testing -- 3.3 The Scan Effective Circuit -- 3.4 The Mux-D Style Scan Flip-Flops -- 3.4.1 The Multiplexed-D Flip-Flop Scan Cell -- 3.4.2 Perceived Silicon Impact of the Mux-D Scan Flip-Flop -- 3.4.3 Other Types of Scan Flip-Flops -- 3.4.4 Mixing Scan Styles -- 3.5 Preferred Mux-D Scan Flip-Flops -- 3.5.1 Operation Priority of the Multiplexed-D Flip-Flop Scan Cell -- 3.5.2 The Mux-D Flip-Flop Family -- 3.6 The Scan Shift Register or Scan Chain -- 3.6.1 The Scan Architecture for Test -- 3.6.2 The Scan Shift Register (a.k.a The Scan Chain) -- 3.7 Scan Cell Operations -- 3.7.1 Scan Cell Transfer Functions -- 3.8 Scan Test Sequencing -- 3.9 Scan Test Timing -- 3.10 Safe Scan Shifting -- 3.11 Safe Scan Sampling: Contention-Free Vectors -- 3.11.1 Contention-Free Vectors -- 3.12 Partial Scan -- 3.12.1 Scan Testing with Partial-Scan -- 3.12.2 Sequential ATPG -- 3.13 Multiple Scan Chains -- 3.13.1 Advantages of Multiple Scan Chains -- 3.13.2 Balanced Scan Chains -- 3.14 The Borrowed Scan Interface -- 3.14.1 Setting up a Borrowed Scan Interface -- 3.14.2 The Shared Scan Input Interface -- 3.14.3 The Shared Scan Output Interface -- 3.15 Clocking, On-Chip Clock Sources, and Scan -- 3.15.1 On-Chip Clock Sources and Scan Testing -- 3.15.2 On-Chip Clocks and Being Scan Tested -- 3.16 Scan-Based Design Rules -- 3.16.1 Scan-Based DFT and Design Rules -- 3.16.2 The Rules -- 3.17 Stuck-At (DC) Scan Insertion -- 3.17.1 DC Scan Insertion -- 3.17.2 Extras -- 3.17.3 DC Scan Insertion and Multiple Clock Domains. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
3.18 Stuck-At Scan Diagnostics -- 3.18.1 Implementing Stuck-At Scan Diagnostics -- 3.18.2 Diagnostic Fault Simulation -- 3.18.3 Functional Scan-Out -- 3.19 At-Speed Scan (AC) Test Goals -- 3.19.1 AC Test Goals -- 3.19.2 Cost Drivers -- 3.20 At-Speed Scan Testing -- 3.20.1 Uses of At-Speed Scan Testing -- 3.20.2 At-Speed Scan Sequence -- 3.20.3 At-Speed Scan versus DC Scan -- 3.21 The At-Speed Scan Architecture -- 3.21.1 At-Speed Scan Interface -- 3.21.2 At-Speed "Safe Shifting" Logic -- 3.21.3 At-Speed Scan Sample Architecture -- 3.22 The At-Speed Scan Interface -- 3.22.1 At-Speed Scan Shift Interface -- 3.22.2 At-Speed Scan Sample Interface -- 3.23 Multiple Clock and Scan Domain Operation -- 3.23.1 Multiple Timing Domains -- 3.24 Scan Insertion and Clock Skew -- 3.24.1 Multiple Clock Domains, Clock Skew, and Scan Insertion -- 3.24.2 Multiple Time Domain Scan Insertion -- 3.25 Scan Insertion for At-Speed Scan -- 3.25.1 Scan Cell Substitution -- 3.25.2 Scan Control Signal Insertion -- 3.25.3 Scan Interface Insertion -- 3.25.4 Other Considerations -- 3.26 Critical Paths for At-Speed Scan -- 3.26.1 Critical Paths -- 3.26.2 Critical Path Selection -- 3.26.3 Path Filtering -- 3.26.4 False Path Content -- 3.26.5 Real Critical Paths -- 3.26.6 Critical Path Scan-Based Diagnostics -- 3.27 Scan-Based Logic BIST -- 3.27.1 Pseudo-Random Pattern Generation -- 3.27.2 Signature Analysis -- 3.27.3 Logic Built-In Self-Test -- 3.27.4 LFSR Science (A Quick Tutorial) -- 3.27.5 X-Management -- 3.27.6 Aliasing -- 3.28 Scan Test Fundamentals Summary -- 3.29 Recommended Reading -- 4 Memory Test Architectures and Techniques -- 4.1 Introduction to Memory Testing -- 4.1.1 Purpose -- 4.1.2 Introduction to Memory Test -- 4.2 Types of Memories -- 4.2.1 Categorizing Memory Types -- 4.3 Memory Organization -- 4.3.1 Types of Memory Organization -- 4.4 Memory Design Concerns. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
4.4.1 Trade-Offs in Memory Design -- 4.5 Memory Integration Concerns -- 4.5.1 Key Issues in Memory Integration -- 4.6 Embedded Memory Testing Methods -- 4.6.1 Memory Test Methods and Options -- 4.7 The Basic Memory Testing Model -- 4.7.1 Memory Testing -- 4.7.2 Memory Test Fault Model -- 4.7.3 Memory Test Failure Modes -- 4.8 The Stuck-At Bit-Cell Based Fault Models -- 4.8.1 Stuck-At Based Memory Bit-Cell Fault Models -- 4.8.2 Stuck-At Fault Exercising and Detection -- 4.9 The Bridging Defect-Based Fault Models -- 4.9.1 Bridging Defect-Based Memory Test Fault Models -- 4.9.2 Linking Defect Memory Test Fault Models -- 4.9.3 Bridging Fault Exercising and Detection -- 4.10 The Decode Fault Model -- 4.10.1 Memory Decode Fault Models -- 4.10.2 Decode Fault Exercising and Detection -- 4.11 The Data Retention Fault -- 4.11.1 Memory Test Data Retention Fault Models -- 4.11.2 DRAM Refresh Requirements -- 4.12 Diagnostic Bit Mapping -- 4.12.1 Memory Test Diagnostics: Bit Mapping -- 4.13 Algorithmic Test Generation -- 4.13.1 Introduction to Algorithmic Test Generation -- 4.13.2 Automatic Test Generation -- 4.13.3 BIST-Based Algorithmic Testing -- 4.14 Memory Interaction with Scan Testing -- 4.14.1 Scan Test Considerations -- 4.14.2 Memory Interaction Methods -- 4.14.3 Input Observation -- 4.14.4 Output Control -- 4.15 Scan Test Memory Modeling -- 4.15.1 Modeling the Memory for ATPG Purposes -- 4.15.2 Limitations -- 4.16 Scan Test Memory Black-Boxing -- 4.16.1 The Memory Black-Boxing Technique -- 4.16.2 Limitations and Concerns -- 4.17 Scan Test Memory Transparency -- 4.17.1 The Memory Transparency Technique -- 4.17.2 Limitations and Concerns -- 4.18 Scan Test Memory Model of The Fake Word -- 4.18.1 The Fake Word Technique -- 4.18.2 Limitations and Concerns -- 4.19 Memory Test Requirements for MBIST -- 4.19.1 Memory Test Organization. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
4.20 Memory Built-In Self-Test Requirements. |
| 590 ## - LOCAL NOTE (RLIN) |
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| Local note |
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2018. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 655 #4 - INDEX TERM--GENRE/FORM |
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| Genre/form data or focus term |
Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Print version: |
| Main entry heading |
Crouch, Alfred L. |
| Title |
Design-For-Test For Digital Ic'S And Embedded Core Systems |
| Place, publisher, and date of publication |
Noida : Pearson India,c1999 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) |
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| Corporate name or jurisdiction name as entry element |
ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5125872">https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5125872</a> |
| Public note |
Click to View |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |