MARC details
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08686nam a22003613i 4500 |
| 001 - CONTROL NUMBER |
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EBC5127435 |
| 003 - CONTROL NUMBER IDENTIFIER |
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MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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20190107112235.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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181231s2006 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9788131743294 |
| Qualifying information |
(electronic bk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(MiAaPQ)EBC5127435 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(Au-PeEL)EBL5127435 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaONFJC)MIL265268 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)816564940 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
MiAaPQ |
| Language of cataloging |
eng |
| Description conventions |
rda |
| -- |
pn |
| Transcribing agency |
MiAaPQ |
| Modifying agency |
MiAaPQ |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Edition number |
23 |
| Classification number |
621.395 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
C.V.S, Rao. |
| 245 10 - TITLE STATEMENT |
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| Title |
Switching Theory And Logic Design. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
1 online resource (334 pages) |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Cover -- Switching Theory and Logic Design -- Copyright -- Preface -- Contents -- Introduction and Number Systems -- Introduction -- The Binary Number System -- Equivalent Numbers in Decimal and Binary Systems -- Powers of 2, Decimal Equivalents and Commonly Used Names -- Decimal to Binary Conversion -- Octal and Hexadecimal Numbers -- Binary Addition and Subtraction -- Representation of Negative Numbers -- Data Representation in Computers -- 1'S and 2'S Complement Arithmetic -- Addition in Computers -- Addition in Computers -- Binary Codes -- 4-Bit Binary Code and Gray Code -- Reflected Codes -- Generation of Reflected Codes -- Binary Codes for Decimal Digits -- Weighted Binary Codes -- Non-weighted Binary Codes -- Error Detection and Correction -- Error Codes for Different Positions -- Single Error Correcting Hamming Code -- Generation of Hamming Code for Decimal Digits -- Illustrating Correction of Received Code Word -- Alphanumeric Codes -- Summary -- Key Words -- Review Questions -- Problems -- Boolean Algebra -- Fundamental Postulates -- Symbols for Switching or Logical Operators -- Definitions of the Binary Operators -- Basic gates -- Basic Properties -- Duality In Boolean Algebra -- Simplification of Boolean Expressions -- Absorption Law -- Redundant Literal Rule -- Involution -- Consensus Theorem -- De Morgan's Theorems -- Complement of a Switching Expression -- Shannon's Expansion Theorem -- Relations between Complement and Dual -- Boolean Functions and their Representation -- Switching cube representation off = x¢ x2 + x2¢ x3 -- Venn diagram representation off = x1¢ x2 + x2¢ x3 -- variable Karnaugh map -- Functionally Complete Sets of Operations -- Properties of Exclusive or -- Functionally Complete Sets of Operators -- Standard Symbols for Logic Gates -- Multi Level Realisation -- A Clever Realisation. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Procedure for Multi Level Nand Realisation -- Summary -- Key Words -- Review Questions -- Problems -- Minimisation of Switching Functions -- Introduction -- The Veitch-Karnaugh Map Method -- Illustrating minimisation of a 4-variable function -- Minimal Sum of Products -- Don't Care Combinations -- Minimal Product of Sums -- Mps form for Functions with Optional Combinations -- quine-mc cluskey tabular method of minimisation -- Prime Implicant Chart -- Algebraic method of finding minimal sets of prime Implicants -- Tabular Method Using Decimal Codes -- Summary -- Review Questions -- Problems -- Design of Combinational Circuits -- Design Using -- Encoder, Decoder, Multiplexer, De-Multiplexera -- Encoder -- Binary Words for Decimal Digits -- Decoder -- Priority Encoder -- Multiplexer -- Demultiplexer -- Modular Design Using Integrated Circuit -- Realisation of Boolean Function Using a Multiplexer -- Parity Bit Generator -- Code Converters -- Magnitude Comparators -- Adders and Subtractors -- Full Subtractor -- Ripple Carry Adder -- Carry-Look-Ahead Adder -- BCD Adder for Decimal Digits -- Programmable Logic Devices -- Programmable Read-only Memory -- Programmable-Logic-Array -- PLA Program Table -- Programmable-Array-Logic -- Programmable Logic Devices-a Comparison -- Hazards and Hazard-Free Realisations -- Static Hazards -- Hazard-free Realisation -- Summary -- Key Words -- Review Questions -- Problems -- Threshold Logic and Symmetric Functions -- Introductory Concepts -- Threshold Gate-Definition and Hardware -- Capabilities of T-Gate -- Universality of T-Gate -- Properties of Threshold Functions -- Separating Function Representation -- Synthesis of Threshold Functions -- Multi-Gate Synthesis -- Limitations of Threshold Gate -- Symmetric Functions and Networks -- Circuit Realisation of Symmetric Functions -- Identification of Symmetric Functions. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Summary -- Key Words -- Review Questions -- Problems -- Flip-Flops as Memory Elements -- Basic Structure of a Flip-Flop -- S-R Flip-Flop -- Clocked S-R Flip-Flop -- J-K Flip-Flop -- Race Around Condition -- Master-Slave J-K Flip-Flop -- Excitation Table for J-K Flip-Flop -- Conversion of J-K Flip-Flop Into T Flip-Flop -- Conversion of J-K Flip-Flop into D Flip-Flop -- Conversion of T to D-FF -- Conversion of D to T FF -- Conversion of T to J-K FF and D to J-K FF -- Conversion of D FF to J-K FF -- Triggering of Flip-Flops -- The D-Latch -- Summary -- Key Words -- Review Questions -- Problems -- Synchronous Sequential Circuits -- Design Steps -- Design Example 1-Modulo-5 Counter -- Design Example 2 -- Design of a Serial Binary Adder -- Model of a Finite State Machine -- Ring Counter and Shift Counters -- Shift Counter -- Decoding in a Shift Counter and Control Pulses -- Register Operations -- Summary -- Key Words -- Review Questions -- Problems -- Asynchronous Sequential Circuits -- Introductory Concepts -- Fundamental Mode Circuits -- Design Example 1 -- Design Example 2 -- Races, Cycles and Valid Assignments -- Essential Hazards in Asynchronous Circuits -- Pulse Mode Asynchronous Circuits -- Design Example 3 -- Asynchronous Pulse Input Counters -- Up-down Counter -- Summary -- Key Words -- Review Questions -- Problems -- Minimisation of Sequential Machines -- Limitations of Finite State Machines -- Machine Identification -- Mealy and Moore Models -- Minimisation -- Partition Technique -- Reduced Standard form State Table -- Merger Chart Method -- State reduction in incompletely specified sequential Machines -- Paull-Unger Method -- Inadequacy of Compatibility Graph -- Bunching Graph -- Generation of Symbolic Compatibles and Prime Closed Sets -- Deletion Theorems and Generation of Symbolic Compatibles -- Reduced Symbolic Compatibles. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Symbolic Vs Prime Compatibles -- Bounds on Minimal Closed Cover -- Existing Upper Bound -- Min-Max Cover -- Upper Bound Using MICs -- Prime closed set-an alternative definition and testing Procedure -- Procedure for Testing Prime Closed Sets -- Procedure for Generation of All Prime Closed Sets -- Simplification of Prime Closed Set Covering Tables -- Prime Closed Set Covering Table -- Simplification Procedure and Solution of Prime Closed Set Covering Tables -- Summary -- Minimal Closed Cover -- Generation of Prime Closed Sets of Symbolic Compatibles and Obtaining aMinimal Closed Cover -- Procedure for Finding a Minimal Closed Cover -- All Minimal Closed Covers -- Summary -- Key Words -- Review Questions -- Problems -- Algorithmic State Machine Charts -- Components of Asm Chart -- Introductory Examples of Asm Charts -- Mod-5 Counter -- Sequence Detector -- Serial Adder -- Salient Features of Asm Chart -- Algorithmic State Machine for Weight Computation -- System Design -- Data Processor Subsystem -- Control Subsystem -- Conventional Hardware Realisation -- Multiplexer Control -- PLA Control -- Algorithmic State Machine for a Binary Multiplier -- Control Subsystem -- PLA Control -- Multiplexer Control -- Summary -- Key Words -- Review Questions -- Problems -- Appendix A: ASCII Code -- Appendix B: Symbolic Compatibles -- Appendix C: Deleted and Excluded Compatibles -- References -- Index. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
Switching Theory and Logic Design is for a first level introductory course on digital logic design. This book illustrates the usefulness of switching theory and its applications, with examples to acquaint the student with necessary background. This book has designed as a prerequisite to many other courses like Digital Integrated Circuits, Computer Organisation, Digital Instrumentation, Digital Control, Digital Communications, Hardware Description Languages and so on. |
| 590 ## - LOCAL NOTE (RLIN) |
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| Local note |
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2018. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 655 #4 - INDEX TERM--GENRE/FORM |
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| Genre/form data or focus term |
Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Print version: |
| Main entry heading |
C.V.S, Rao |
| Title |
Switching Theory And Logic Design |
| Place, publisher, and date of publication |
Noida : Pearson India,c2006 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) |
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| Corporate name or jurisdiction name as entry element |
ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5127435">https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5127435</a> |
| Public note |
Click to View |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |