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08344nam a22003613i 4500 |
| 001 - CONTROL NUMBER |
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EBC5127072 |
| 003 - CONTROL NUMBER IDENTIFIER |
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MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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20190107153504.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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181231s2009 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9788131740392 |
| Qualifying information |
(electronic bk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(MiAaPQ)EBC5127072 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(Au-PeEL)EBL5127072 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaONFJC)MIL262893 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)1024287086 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
MiAaPQ |
| Language of cataloging |
eng |
| Description conventions |
rda |
| -- |
pn |
| Transcribing agency |
MiAaPQ |
| Modifying agency |
MiAaPQ |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Edition number |
23 |
| Classification number |
004 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Stallings, William. |
| 245 10 - TITLE STATEMENT |
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| Title |
Computer Organization and Architecture. |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
8th ed. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
1 online resource (881 pages) |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Cover -- Contents -- Web Site for the Book -- About the Author -- Preface -- Chapter 0 Reader's Guide -- 0.1 Outline of the Book -- 0.2 A Roadmap for Readers and Instructors -- 0.3 Why Study Computer Organization and Architecture -- 0.4 Internet and Web Resources -- PART ONE: OVERVIEW -- Chapter 1 Introduction -- 1.1 Organization and Architecture -- 1.2 Structure and Function -- 1.3 Key Terms and Review Questions -- Chapter 2 Computer Evolution and Performance -- 2.1 A Brief History of Computers -- 2.2 Designing for Performance -- 2.3 The Evolution of the Intel x86 Architecture -- 2.4 Embedded Systems and the ARM -- 2.5 Performance Assessment -- 2.6 Recommended Reading and Web Sites -- 2.7 Key Terms, Review Questions, and Problems -- PART TWO: THE COMPUTER SYSTEM -- Chapter 3 A Top-Level View of Computer Function and Interconnection -- 3.1 Computer Components -- 3.2 Computer Function -- 3.3 Interconnection Structures -- 3.4 Bus Interconnection -- 3.5 PCI -- 3.6 Recommended Reading and Web Sites -- 3.7 Key Terms, Review Questions, and Problems -- Appendix 3A: Timing Diagrams -- Chapter 4 Cache Memory -- 4.1 Computer Memory System Overview -- 4.2 Cache Memory Principles -- 4.3 Elements of Cache Design -- 4.4 Pentium 4 Cache Organization -- 4.5 ARM Cache Organization -- 4.6 Recommended Reading -- 4.7 Key Terms, Review Questions, and Problems -- Appendix 4A: Performance Characteristics of Two-Level Memories -- Chapter 5 Internal Memory Technology -- 5.1 Semiconductor Main Memory -- 5.2 Error Correction -- 5.3 Advanced DRAM Organization -- 5.4 Recommended Reading and Web Sites -- 5.5 Key Terms, Review Questions, and Problems -- Chapter 6 External Memory -- 6.1 Magnetic Disk -- 6.2 RAID -- 6.3 Optical Memory -- 6.4 Magnetic Tape -- 6.5 Recommended Reading and Web Sites -- 6.6 Key Terms, Review Questions, and Problems -- Chapter 7 Input/Output. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
7.1 External Devices -- 7.2 I/O Modules -- 7.3 Programmed I/O -- 7.4 Interrupt-Driven I/O -- 7.5 Direct Memory Access -- 7.6 I/O Channels and Processors -- 7.7 The External Interface: FireWire and Infiniband -- 7.8 Recommended Reading and Web Sites -- 7.9 Key Terms, Review Questions, and Problems -- Chapter 8 Operating System Support -- 8.1 Operating System Overview -- 8.2 Scheduling -- 8.3 Memory Management -- 8.4 Pentium Memory Management -- 8.5 ARM Memory Management -- 8.6 Recommended Reading and Web Sites -- 8.7 Key Terms, Review Questions, and Problems -- PART THREE: THE CENTRAL PROCESSING UNIT -- Chapter 9 Computer Arithmetic -- 9.1 The Arithmetic and Logic Unit (ALU) -- 9.2 Integer Representation -- 9.3 Integer Arithmetic -- 9.4 Floating-Point Representation -- 9.5 Floating-Point Arithmetic -- 9.6 Recommended Reading and Web Sites -- 9.7 Key Terms, Review Questions, and Problems -- Chapter 10 Instruction Sets: Characteristics and Functions -- 10.1 Machine Instruction Characteristics -- 10.2 Types of Operands -- 10.3 Intel x86 and ARM Data Types -- 10.4 Types of Operations -- 10.5 Intel x86 and ARM Operation Types -- 10.6 Recommended Reading -- 10.7 Key Terms, Review Questions, and Problems -- Appendix 10A: Stacks -- Appendix 10B: Little, Big, and Bi-Endian -- Chapter 11 Instruction Sets: Addressing Modes and Formats -- 11.1 Addressing -- 11.2 x86 and ARM Addressing Modes -- 11.3 Instruction Formats -- 11.4 x86 and ARM Instruction Formats -- 11.5 Assembly Language -- 11.6 Recommended Reading -- 11.7 Key Terms, Review Questions, and Problems -- Chapter 12 Processor Structure and Function -- 12.1 Processor Organization -- 12.2 Register Organization -- 12.3 The Instruction Cycle -- 12.4 Instruction Pipelining -- 12.5 The x86 Processor Family -- 12.6 The ARM Processor -- 12.7 Recommended Reading -- 12.8 Key Terms, Review Questions, and Problems. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Chapter 13 Reduced Instruction Set Computers (RISCs) -- 13.1 Instruction Execution Characteristics -- 13.2 The Use of a Large Register File -- 13.3 Compiler-Based Register Optimization -- 13.4 Reduced Instruction Set Architecture -- 13.5 RISC Pipelining -- 13.6 MIPS R4000 -- 13.7 SPARC -- 13.8 The RISC versus CISC Controversy -- 13.9 Recommended Reading -- 13.10 Key Terms, Review Questions, and Problems -- Chapter 14 Instruction-Level Parallelism and Superscalar Processors -- 14.1 Overview -- 14.2 Design Issues -- 14.3 Pentium 4 -- 14.4 ARM Cortex-A8 -- 14.5 Recommended Reading -- 14.6 Key Terms, Review Questions, and Problems -- PART FOUR: THE CONTROL UNIT -- Chapter 15 Control Unit Operation -- 15.1 Micro-operations -- 15.2 Control of the Processor -- 15.3 Hardwired Implementation -- 15.4 Recommended Reading -- 15.5 Key Terms, Review Questions, and Problems -- Chapter 16 Microprogrammed Control -- 16.1 Basic Concepts -- 16.2 Microinstruction Sequencing -- 16.3 Microinstruction Execution -- 16.4 TI 8800 -- 16.5 Recommended Reading -- 16.6 Key Terms, Review Questions, and Problems -- PART FIVE: PARALLEL ORGANIZATION -- Chapter 17 Parallel Processing -- 17.1 The Use of Multiple Processors -- 17.2 Symmetric Multiprocessors -- 17.3 Cache Coherence and the MESI Protocol -- 17.4 Multithreading and Chip Multiprocessors -- 17.5 Clusters -- 17.6 Nonuniform Memory Access Computers -- 17.7 Vector Computation -- 17.8 Recommended Reading and Web Sites -- 17.9 Key Terms, Review Questions, and Problems -- Chapter 18 Multicore Computers -- 18.1 HardwarePerformance Issues -- 18.2 Software Performance Issues -- 18.3 Multicore Organization -- 18.4 Intel x86 Multicore Organization -- 18.5 ARM11 MPCore -- 18.6 Recommended Reading and Web Sites -- 18.7 Key Terms, Review Questions, and Problems -- Appendix A: Projects for Teaching Computer Organization and Architecture. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
A.1 Interactive Simulations -- A.2 Research Projects -- A.3 Simulation Projects -- A.4 Assembly Language Projects -- A.5 Reading/Report Assignments -- A.6 Writing Assignments -- A.7 Test Bank -- Appendix B: Assembly Language and Related Topics -- B.1 Assembly Language -- B.2 Assemblers -- B.3 Loading and Linking -- B.4 Recommended Reading and Web Sites -- B.5 Key Terms, Review Questions, and Problems -- ONLINE CHAPTERS -- Chapter 19 Number Systems -- 19.1 The Decimal System -- 19.2 The Binary System -- 19.3 Converting between Binary and Decimal -- 19.4 Hexadecimal Notation -- 19.5 Key Terms, Review Questions, and Problems -- Chapter 20 Digital Logic -- 20.1 Boolean Algebra -- 20.2 Gates -- 20.3 Combinational Circuits -- 20.4 Sequential Circuits -- 20.5 Programmable Logic Devices -- 20.6 Recommended Reading and Web Site -- 20.7 Key Terms and Problems -- Chapter 21 The IA-64 Architecture -- 21.1 Motivation -- 21.2 General Organization -- 21.3 Predication, Speculation, and Software Pipelining -- 21.4 IA-64 Instruction Set Architecture -- 21.5 Itanium Organization -- 21.6 Recommended Reading and Web Sites -- 21.7 Key Terms, Review Questions, and Problems -- Glossary -- A -- B -- C -- D -- E -- F -- G -- H -- I -- K -- L -- M -- N -- O -- P -- R -- S -- T -- U -- V -- W -- References -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- Q -- R -- S -- T -- U -- V -- W. |
| 590 ## - LOCAL NOTE (RLIN) |
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| Local note |
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2018. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 655 #4 - INDEX TERM--GENRE/FORM |
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| Genre/form data or focus term |
Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Print version: |
| Main entry heading |
Stallings, William |
| Title |
Computer Organization and Architecture: Designing for Performance, CourseSmart eTextbook |
| Place, publisher, and date of publication |
: Pearson India,c2009 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) |
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| Corporate name or jurisdiction name as entry element |
ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5127072">https://ebookcentral.proquest.com/lib/cethalassery/detail.action?docID=5127072</a> |
| Public note |
Click to View |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |