FPGA-Based System Design.

Cover -- Contents -- Preface -- Chapter 1 FPGA-Based Systems -- 1.1 Introduction -- 1.2 Basic Concepts -- 1.2.1 Boolean Algebra -- 1.2.2 Schematics and Logic Symbols -- 1.3 Digital Design and FPGAs -- 1.3.1 The Role of FPGAs -- 1.3.2 FPGA Types -- 1.3.3 FPGAs vs. Custom VLSI -- 1.4 FPGA-Based System Design -- 1.4.1 Goals and Techniques -- 1.4.2 Hierarchical Design -- 1.4.3 Design Abstraction -- 1.4.4 Methodologies -- 1.5 Summary -- 1.6 Problems -- Chapter 2 VLSI Technology -- 2.1 Introduction -- 2.2 Manufacturing Processes -- 2.3 Transistor Characteristics -- 2.4 CMOS Logic Gates -- 2.4.1 Static Complementary Gates -- 2.4.2 Gate Delay -- 2.4.3 Power Consumption -- 2.4.4 Driving Large Loads -- 2.4.5 Low-Power Gates -- 2.4.6 Switch Logic -- 2.5 Wires -- 2.5.1 Wire Structures -- 2.5.2 Wire Parasitics -- 2.5.3 Models for Wires -- 2.5.4 Delay Through an RC Transmission Line -- 2.5.5 Buffer Insertion in RC Transmission Lines -- 2.5.6 Crosstalk Between RC Wires -- 2.6 Registers and RAM -- 2.6.1 Register Structures -- 2.6.2 Random-Access Memory -- 2.7 Packages and Pads -- 2.7.1 Packages -- 2.7.2 Pads -- 2.8 Summary -- 2.9 Problems -- Chapter 3 FPGA Fabrics -- 3.1 Introduction -- 3.2 FPGA Architectures -- 3.3 SRAM-Based FPGAs -- 3.3.1 Overview -- 3.3.2 Logic Elements -- 3.3.3 Interconnection Networks -- 3.3.4 Configuration -- 3.4 Permanently Programmed FPGAs -- 3.4.1 Antifuses -- 3.4.2 Flash Configuration -- 3.4.3 Logic Blocks -- 3.4.4 Interconnection Networks -- 3.4.5 Programming -- 3.5 Chip I/O -- 3.6 Circuit Design of FPGA Fabrics -- 3.6.1 Logic Elements -- 3.6.2 Interconnect -- 3.7 Architecture of FPGA Fabrics -- 3.7.1 Logic Element Parameters -- 3.7.2 Interconnect Architecture -- 3.7.3 Pinout -- 3.8 Summary -- 3.9 Problems -- Chapter 4 Combinational Logic -- 4.1 Introduction -- 4.2 The Logic Design Process -- 4.3 Hardware Description Languages.

4.3.1 Modeling with HDLs -- 4.3.2 Verilog -- 4.3.3 VHDL -- 4.4 Combinational Network Delay -- 4.4.1 Delay Specifications -- 4.4.2 Gate and Wire Delay -- 4.4.3 Fanout -- 4.4.4 Path Delay -- 4.4.5 Delay and Physical Design -- 4.5 Power and Energy Optimization -- 4.5.1 Glitching Analysis and Optimization -- 4.6 Arithmetic Logic -- 4.6.1 Number Representations -- 4.6.2 Combinational Shifters -- 4.6.3 Adders -- 4.6.4 ALUs -- 4.6.5 Multipliers -- 4.7 Logic Implementation for FPGAs -- 4.7.1 Syntax-Directed Translation -- 4.7.2 Logic Implementation by Macro -- 4.7.3 Logic Synthesis -- 4.7.4 Technology-Independent Logic Optimization -- 4.7.5 Technology-Dependent Logic Optimizations -- 4.7.6 Logic Synthesis for FPGAs -- 4.8 Physical Design for FPGAs -- 4.8.1 Placement -- 4.8.2 Routing -- 4.9 The Logic Design Process Revisited -- 4.10 Summary -- 4.11 Problems -- Chapter 5 Sequential Machines -- 5.1 Introduction -- 5.2 The Sequential Machine Design Process -- 5.3 Sequential Design Styles -- 5.3.1 State Transition and Register-Transfer Models -- 5.3.2 Finite-State Machine Theory -- 5.3.3 State Assignment -- 5.3.4 Verilog Modeling Styles -- 5.4 Rules for Clocking -- 5.4.1 Flip-Flops and Latches -- 5.4.2 Clocking Disciplines -- 5.5 Performance Analysis -- 5.5.1 Performance of Flip-Flop-Based Systems -- 5.5.2 Performance of Latch-Based Systems -- 5.5.3 Clock Skew -- 5.5.4 Retiming -- 5.6 Power Optimization -- 5.7 Summary -- 5.8 Problems -- Chapter 6 Architecture -- 6.1 Introduction -- 6.2 Behavioral Design -- 6.2.1 Data Path-Controller Architectures -- 6.2.2 Scheduling and Allocation -- 6.2.3 Power -- 6.2.4 Pipelining -- 6.3 Design Methodologies -- 6.3.1 Design Processes -- 6.3.2 Design Standards -- 6.3.3 Design Verification -- 6.4 Design Example -- 6.4.1 Digital Signal Processor -- 6.5 Summary -- 6.6 Problems -- Chapter 7 Large-Scale Systems -- 7.1 Introduction.

7.2 Busses -- 7.2.1 Protocols and Specifications -- 7.2.2 Logic Design for Busses -- 7.2.3 Microprocessor and System Busses -- 7.3 Platform FPGAs -- 7.3.1 Platform FPGA Architectures -- 7.3.2 Serial I/O -- 7.3.3 Memories -- 7.3.4 CPUs and Embedded Multipliers -- 7.4 Multi-FPGA Systems -- 7.4.1 Constraints on Multi-FPGA Systems -- 7.4.2 Interconnecting Multiple FPGAs -- 7.4.3 Multi-FPGA Partitioning -- 7.5 Novel Architectures -- 7.5.1 Machines Built From FPGAs -- 7.5.2 Alternative FPGA Fabrics -- 7.6 Summary -- 7.7 Problems -- Appendix A: Glossary -- A -- B -- C -- D -- E -- F -- G -- H -- I -- L -- M -- N -- O -- P -- R -- S -- T -- U -- V -- W -- X -- Appendix B: Hardware Description Languages -- B.1 Introduction -- B.2 Verilog -- B.2.1 Syntactic Elements -- B.2.2 Data Types and Declarations -- B.2.3 Operators -- B.2.4 Statements -- B.2.5 Modules and Program Units -- B.2.6 Simulation Control -- B.3 VHDL -- B.3.1 Syntactic Elements -- B.3.2 Data Types and Declarations -- B.3.3 Operators -- B.3.4 Sequential Statements -- B.3.5 Structural Statements -- B.3.6 Design Units -- B.3.7 Processes -- References -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- Q -- R -- S -- T -- U -- V -- W -- X -- Y.

Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2018. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.