Cover -- Contents -- About This Book -- The MindShare Architecture Series -- Organization of This Book -- Designation of Specification Changes -- Cautionary Note -- Who this Book is For -- Prerequisite Knowledge -- Object Size Designations -- Documentation Conventions -- Hex Notation -- Binary Notation -- Decimal Notation -- Signal Name Representation -- Identification of Bit Fields (logical groups of bits or signals) -- We Want Your Feedback -- Chapter 1: Intro To PCI -- PCI Bus History -- PCI Bus Features -- PCI Device vs. Function -- Specifications Book is Based On -- Obtaining PCI Bus Specification(s) -- Chapter 2: Intro to PCI Bus Operation -- Burst Transfer -- Initiator, Target and Agents -- Single- Vs. Multi-Function PCI Devices -- PCI Bus Clock -- Address Phase -- Claiming the Transaction -- Data Phase(s) -- Transaction Duration -- Transaction Completion and Return of Bus to Idle State -- Response to Illegal Behavior -- Green" Machine -- Chapter 3: Intro to Reflected-Wave Switching -- Each Trace Is a Transmission Line -- Old Method: Incident- Wave Switching -- PCI Method: Reflected- Wave Switching -- CLK Signal -- RST#/REQ64# Timing -- Slower Clock Permits Longer Bus -- Chapter 4: The Signal Groups -- Introduction -- System Signals -- PCI Clock Signal (CLK) -- CLKRUN# Signal -- Reset Signal (RST#) -- Address/ Data Bus, Command Bus, and Byte Enables -- Preventing Excessive Current Drain -- Transaction Control Signals -- Arbitration Signals -- Interrupt Request Signals -- Error Reporting Signals -- Data Parity Error -- System Error -- Cache Support (Snoop Result) Signals -- 64-bit Extension Signals -- Resource Locking -- JTAG/Boundary Scan Signals -- Interrupt Request Pins -- PME# and 3.3Vaux -- Sideband Signals -- Signal Types -- Device Cannot Simultaneously Drive and Receive a Signal -- Central Resource Functions.

Subtractive Decode (by ISA Bridge) -- Background -- Tuning Subtractive Decoder -- Reading Timing Diagrams -- Chapter 5: PCI Bus Arbitration -- Arbiter -- Arbitration Algorithm -- Example Arbiter with Fairness -- Master Wishes To Perform More Than One Transaction -- Hidden Bus Arbitration -- Bus Parking -- Request/Grant Timing -- Example of Arbitration Between Two Masters -- State of REQ# and GNT# During RST# -- Pullups On REQ# From Add-In Connectors -- Broken Master -- Chapter 6: Master and Target Latency -- Mandatory Delay Before First Transaction Initiated -- Bus Access Latency -- Pre-2.1 Devices Can Be Bad Boys -- Preventing Master from Monopolizing the Bus -- Master Must Transfer Data Within 8 CLKs -- IRDY# Deasserted In Clock After Last Data Transfer -- Latency Timer Keeps Master From Monopolizing Bus -- Preventing Target From Monopolizing Bus -- General -- Target Must Transfer Data Expeditiously -- Target Latency During Initialization Time -- Delayed Transactions -- Posting Improves Memory Write Performance -- General -- Combining -- Byte Merging -- Collapsing Is Forbidden -- Memory Write Maximum Completion Limit -- Transaction Ordering and Deadlocks -- Chapter 7: The Commands -- Introduction -- Interrupt Acknowledge Command -- Introduction -- Background -- Host/PCI Bridge Handling of Interrupt Acknowledge -- PCI Interrupt Acknowledge Transaction -- PowerPC PReP Handling of INTR -- Special Cycle Command -- General -- Special Cycle Generation Under Software Control -- Special Cycle Transaction -- IO Read and Write Commands -- Accessing Memory -- Target Support For Bulk Commands Is Optional -- Cache Line Size Register And the Bulk Commands -- Bulk Commands Are Optional Performance Enhancement Tools -- Bridges Must Discard Prefetched Data Not Consumed By Master -- Writing Memory -- More Information On Memory Transfers.

Configuration Read and Write Commands -- Dual-Address Cycle -- Reserved Bus Commands -- Chapter 8: Read Transfers -- Some Basic Rules For Both Reads and Writes -- Parity -- Example Single Data Phase Read -- Example Burst Read -- Treatment of Byte Enables During Read or Write -- Byte Enables Presented on Entry To Data Phase -- Byte Enables May Change In Each Data Phase -- Data Phase with No Byte Enables Asserted -- Target with Limited Byte Enable Support -- Rule for Sampling of Byte Enables -- Cases Where Byte Enables Can Be Ignored -- Performance During Read Transactions -- Chapter 9: Write Transfers -- Example Single Data Phase Write Transaction -- Example Burst Write Transaction -- Performance During Write Transactions -- Chapter 10: Memory and IO Addressing -- Memory Addressing -- The Start Address -- Addressing Sequence During Memory Burst -- PCI IO Addressing -- Do Not Merge Processor IO Writes -- General -- Decode By Device That Owns Entire IO Dword -- Decode by Device With 8- Bit or 16-Bit Ports -- Unsupported Byte Enable Combination Results in Target Abort -- Null First Data Phase Is Legal -- IO Address Management -- When IO Target Doesn't Support Multi-Data Phase Transactions -- Legacy IO Decode -- Chapter 11: Fast Back-to-Back & Stepping -- Fast Back-to-Back Transactions -- Decision to Implement Fast Back-to-Back Capability -- Scenario 1: Master Guarantees Lack of Contention -- Scenario Two: Targets Guarantee Lack of Contention -- Address/Data Stepping -- Advantages: Diminished Current Drain and Crosstalk -- Why Targets Don't Latch Address During Stepping Process -- Data Stepping -- How Device Indicates Ability to Use Stepping -- Designer May Step Address, Data, PAR ( and PAR64) and IDSEL -- Continuous and Discrete Stepping -- Disadvantages of Stepping -- Preemption While Stepping in Progress -- Broken Master -- Stepping Example.

When Not to Use Stepping -- Who Must Support Stepping? -- Chapter 12: Early Transaction End -- Introduction -- Master-Initiated Termination -- Master Preempted -- Introduction -- Preemption During Timeslice -- Timeslice Expiration Followed by Preemption -- Master Abort: Target Doesn't Claim Transaction -- Introduction -- Addressing Non-Existent Device -- Normal Response To Special Cycle Transaction -- Configuration Transaction Unclaimed -- No Target Will Claim Transaction Using Reserved Command -- Master Abort On Single vs. Multiple-Data Phase Transaction -- Master Abort on Single Data Phase Transaction -- Master Abort on Multi-Data Phase Transaction -- Action Taken by Master in Response to Master Abort -- Target-Initiated Termination -- STOP# Signal Puts Target In the Driver's Seat -- STOP# Not Permitted During Turn-Around Cycle -- Disconnect -- Retry -- Target Abort -- After Retry/Disconnect, Repeat Request ASAP -- Target-Initiated Termination Summary -- Chapter 13: Error Detection and Handling -- Status Bit Name Change -- Introduction to PCI Parity -- PERR# Signal -- Data Parity -- Data Parity Generation and Checking on Read -- Data Parity Generation and Checking on Write -- Data Parity Reporting -- Data Parity Error Recovery -- Special Case: Data Parity Error During Special Cycle -- Devices Excluded from PERR# Requirement -- SERR# Signal -- Address Phase Parity -- System Errors -- Chapter 14: Interrupts -- Three Ways To Deliver Interrupts To Processor -- Using Pins vs. Using MSI Capability -- Single- Function PCI Device -- Multi- Function PCI Device -- Connection of INTx# Pins To System Board Traces -- Interrupt Routing -- General -- Routing Recommendation In PCI Specification -- BIOS "Knows" Interrupt Trace Layout -- Well-Designed Chipset Has Programmable Interrupt Router -- Interrupt Routing Information -- Interrupt Routing Table -- General.

Finding the Table -- PCI Interrupts Are Shareable -- Hooking the Interrupt -- Interrupt Chaining -- General -- Step 1: Initialize All Entries To Point To Dummy Handler -- Step 2: Initialize All Entries For Embedded Devices -- Step 3: Hook Entries For Embedded Device BIOS Routines -- Step 4: Perform Expansion Bus ROM Scan -- Step 5: Perform PCI Device Scan -- Step 6: Load OS -- Step 7: OS Loads and Call Drivers' Initialization Code -- Linked-List Has Been Built for Each Interrupt Level -- Servicing Shared Interrupts -- Example Scenario -- Both Devices Simultaneously Generate Requests -- Processor Interrupted and Requests Vector -- First Handler Executed -- Jump to Next Driver in Linked List -- Jump to Dummy Handler: Control Passed Back to Interrupted Program -- Implied Priority Scheme -- Interrupts and PCI-to-PCI Bridges -- Message Signaled Interrupts ( MSI) -- Introduction -- Advantages of MSI Interrupts -- Basics of MSI Configuration -- Basics of Generating an MSI Interrupt Request -- How Is the Memory Write Treated by Bridges? -- Memory Already Sync'd When Interrupt Handler Entered -- Interrupt Latency -- MSI Are Non-Shared -- MSI Is a New Capability Type -- Description of the MSI Capability Register Set -- Message Write Can Have Bad Ending -- Some Rules, Recommendations, etc -- Chapter 15: The 64-bit PCI Extension -- 64-bit Data Transfers and 64-bit Addressing: Separate Capabilities -- 64-Bit Extension Signals -- 64-bit Cards in 32-bit Add-in Connectors -- Pullups Prevent 64-bit Extension from Floating When Not in Use -- Problem: a 64-bit Card in a 32-bit PCI Connector -- How 64-bit Card Determines Type of Slot Installed In -- 64-bit Data Transfer Capability -- Only Memory Commands May Use 64-bit Transfers -- Start Address Quadword-Aligned -- 64-bit Initiator and 64-bit Target -- 64-bit Initiator and 32-bit Target -- Null Data Phase Example.

32-bit Initiator and 64-bit Target.

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